The present invention relates to managing the power consumption of an integrated circuit, especially a large-scale integrated circuit, using clock signal conditioning.
A system clock signal is often used by digital circuitry, such as digital circuitry implemented using an LSI circuit, to synchronously execute certain logic functions. For example, ultra-deep sub-micron (UDSM) microprocessors employ digital circuitry that uses system clock signals to synchronously execute logic functions. These microprocessors operate at system clock frequencies in excess of 1 GHz. The system clock signal of a given LSI circuit is often split into many paths to service different portions of the digital circuitry. Ideally, the system clock signals at different portions of the digital circuitry exhibit exactly the same timing characteristics so that the different portions of the digital circuitry operate in exact synchronization.
FIG. 1 illustrates a conventional clock distribution circuit 10, which includes a clock source 12, a plurality of buffers 14 (e.g., inverters), and a clock distribution tree 16 for transferring the clock signal on 18A to all areas of an LSI chip.
With reference to FIG. 2A, a conventional approach to reducing power dissipation in the LSI chip is to include a slow mode of operation, where the frequency of the clock signal (at the output) delivered to the different areas of the LSI chip is significantly lowered—while maintaining the pulse width of the “on” pulse as if in a fast mode of operation (short on-time). In other words, the off pulse of the clock signal is stretched to reduce the frequency, while maintaining the on pulse. The reason to maintain the short on-time is because many logic circuits (especially dynamic circuits) would not operate properly if long on-time clock signals were employed.
The first approach to producing the slow mode clock signal at the output is to gate the clock signal 18E at the end of the distribution tree 16 to stretch the off pulse. This is accomplished using a clock gating signal 2A and a plurality of gate circuits (not shown). The control signal 2A is used to gate (i.e., remove or mask) a number of the on-pulses of successive periods of the clock signal on 18E. A disadvantage of this approach is that it requires that the buffers 14 and the clock distribution tree 16 carry the high frequency clock from the clock source 12 to the end of the distribution tree 16. This disadvantageously results in the power dissipation of the clock distribution circuit 10 being the same in the slow and fast modes.
A second approach to producing the slow mode clock signal at the output is to stretch the off pulse of the clock signal 18A at the clock source 12. This may be accomplished by using a clock gating signal 2B (which looks the same as clock gating signal 2A), except a single gate circuit (not shown) is used at the source. The control signal 2B is used to gate (i.e., remove or mask) a number of the on-pulses of successive periods of the clock signal on 18A, resulting in a waveform at the output of the circuit 10 that looks substantially the same as the waveform in FIG. 2B. While this second approach reduces the power dissipation in the distribution circuit, both PBTI (positive bias temperature instability) and NBTI (negative bias temperature instability) degradation results within the distribution circuit. (PBTI and NBTI are long-term degradation concerns.) These circuit degradations result because certain of the gates experience negative or positive bias conditions for significantly longer periods that other gates in the LSI. In particular, the clock signals on line 18A, 18B, 18C, etc., have 1/10 units of on-time and 9/10 units of off-time each period. The intervening clock signals (between 18A, 18B, 18C, etc.) have 9/10 units of on-time and 1/10 units of off-time each period. Thus, disadvantageously, design margins must be employed to account for PBTI and/or NBTI.
In view of the above, the conventional techniques for reducing power consumption by way of a slow mode of operation have been unsatisfactory. Accordingly, there is a need in the art for a new and better solution to the problem, which preferably does not require the power dissipation of the clock distribution circuit being the same in the slow and fast modes, and does not result in PBTI and/or NBTI.